In order to explain the background of the invention in detail, reference will be particularly made to FIG. 5 which shows a construction of a prior art parallel-input, parallel-output shift register:
In FIG. 5, the reference numeral 1 designates a shift register of bit length l including a first, second, third, . . . , (l-2)th, (l-1)th, and l-th cells (2, 3, 4, 5, 6, and 7). The first cell 2 is provided with a data input terminal 8 and a data output terminal 14. The second to l-th cell 3 to 7 are provided with data input terminals 9 to 13 and data output terminals 15 to 19, respectively.
A data input control terminal 20 is provided for controlling the data input from the data input terminals 8 to 13 to cells 2 to 7 of the shift register 1, in addition to a shift control terminal 21 for controlling the shift of data stored in cells 2 to 7, and a data output control terminal 22 for reading out the data stored in cells 2 to 7 of the shift register 1.
FIG. 6 shows an example of a construction of cells 2 to 7 of the shift register 1 where symbols for N channel MOSFETs and logic circuits are used for illustration. This shows an example of a cell of the shift register conducting a shift in only one direction.
The reference numeral 23 designates a cell constituting a shift register 1. The number 24 designates a data input terminal of the cell 23 corresponding to the terminals 8 to 13 of FIG. 5, and the numeral 25 designates a data output terminal of the cell 23 corresponding to the terminals 14 to 19 of FIG. 5. The cell 23 is provided with a shift data input terminal 26 and a shift data output terminal 27. The data from the shift data output terminal of the cell at the former stage is input to the shift data input terminal 26 of the particular cell, and the data from the shift data output terminal 27 of the particular cell is input to the shift data input terminal of the cell at the next stage. When the cell 23 is used as the first cell 2, an arbitrary data is input to the shift data input terminal 26. When it is used as the l-th cell 7, the shift data output terminal 27 is made open. There is provided an inverter 28 which receives a signal input to the shift control terminal 21 and outputs a latched signal 29.
There are provided transfer gates 30 to 34 each constituted by N channel enhancement type MOS FETs. One end of each of the transfer gates 30 to 32 are connected to the node 35, and one end of both of the transfer gates 33 and 34 are connected to the node 37. The one ends of the transfer gate 30 and 31 are connected to the data input terminal 24 and the shift data input terminal 26, respectively. The other ends of the transfer gates 32 and 33 are connected to the node 36, and the other end of the transfer gate 34 is connected to the node 38.
The signal of the node 38 is output of the data output terminal 25 and the shift data output terminal 27. The signal input to the data input control terminal 20 is input to the gate of the transfer gate 30, and the signal input to the shift control terminal 21 is input to the gates of the transfer gates 31 and 34, and the latched signal 29 is input to the gates of the transfer gates 32 and 33.
There are provided two inverters 39 and 40 connected in series to each other. The inverter 39 receives the signal at the node 35, and the output thereof is connected to the input of the inverter 40. The output of the inverter 40 is connected to the node 36. There are also provided two inverters 41 and 42 connected in series to each other. The inverter 41 receives the signal of the node 37, and the output thereof is connected to the input of the inverter 42. The output of the inverter 42 is connected to the node 38.
In this way, the cell 23 of a 2-input latch type shift register is constituted by transfer gates 30 to 34 and inverters 39 to 42. The the data input control signal input to the terminal 20, the shift control signal input to the terminal 21, and the latched signal 29 are commonly used through all of the cells.
This shift register is operated as follows:
In the following description positive logic is used, and the positive logic state is represented by "1", while the non-positive logic state is represented by "0".
In FIG. 6, if a signal input to the shift control terminal 21 is kept "0", the cell 23 becomes a latching state, and the shift register 1 does not conduct a shift operation. Then if the signal input to the data input control terminal 20 is made "1" and data is input from the data input terminal 24 with a driving force enough to change the latching state, the input data is latched at the cell 23. Thereafter, if the signal input to the data input control terminal 20 is made "0" and "1" is input to the shift control terminal 21, the data is shifted by one bit.
FIG. 7 diagrammatically shows the operation of the shift register of FIG. 6, especially showing the movement of the shifted data clearly. FIG. 7(a) shows a 6-bit shift register 43 including a first to a sixth cell arranged from the left to the right. FIG. 7(a) shows a state where the data A, B, . . . , F are set into the 6-bit shift register 43 from the left to the right. When signal "1" is input to the shift data input terminal 26 of the first cell and 2 bits are shifted to the right side, it results in the state shown in FIG. 7(b).
In order to conduct a 2-bit shift as described above it is necessary to input "1" two times to the shift control terminal 21. Similary, it is generally necessary to input a shift control signal n times in order to conduct an n-bit shift, and then it is furthermore necessary to control the shift number.
Furthermore, it is necessary to input a shift control signal to each cell in order to move only three bits of B to D among A to F to the right by one bit with no changes in the states of A to F because the content of all the cells usually changes by the shift operation. In any case, it is only possible to conduct a 1-bit shift in a shift, resulting in difficulty in a high speed operation especially in a shift register of large bit number.
FIG. 8 shows a so-called barrel shifter which has an improvement over the above-described problem where it is required that n pieces of shift control signals be used in an n bit shift. In this barrel shifter all the bits can be transmitted at one time.
FIG. 8 shows an example of construction of a 4-bit barrel shifter constituted by N channel enhancement type MOS FETs. This barrel shifter involves only one direction shift, and no rotation function. The circuit section for latching input data and the control section related to the shift control signal are not shown.
There are provided a first to fourth data input terminals 44 to 47, and a first to fourth data output terminals 48 to 51. There are further provided 0th bit, 1st bit, 2nd bit, and 3rd bit shift control terminals 52 to 55, and transfer gates 56 to 65.
The transfer gate 56 is connected between the first data input terminal 44 and the first data output terminal 48. Similarly as above, the transfer gate 57, 58, 59, 60, 61, 62, 63, 64, and 65 are connected between the terminals 45 and 49, between 46 and 50, 47 and 51, 44, and 49, 45 and 50, 46 and 51, 44 and 50, 45 and 51, and 44 and 51, respectively.
The 0th bit shift control terminal 52 is connected to the gates of the transfer gates 56 to 59, and the 1st bit, 2nd bit, 3rd bit shift control terminal 53, 54, and 55 are connected to the gates of the transfer gates 60 to 62, 63 and 64, and 65, respectively.
This barrel shifter shown in FIG. 8, is operated as follows:
The data of 4 bits to be shifted is input to the data input terminals 44 to 47. Then, "0" is input to each of the bit shift control terminals 52 to 55. Thereafter, when, for example, a 2-bit shift is conducted, the 2-bit shift control terminal 54 is made "1". Thus, the data input to the first data input terminal 44 is output to the third data output terminal 50 through the transfer gate 63. The data input to the second data input terminal 45 is output to the fourth data output terminal 51 through the transfer gate 64. Then the states of the first data output terminal 48 and the second data output terminal 49 are not determined.
As described above, in the barrel shifter shown in FIG. 8, it is possible to conduct an n-bit shift by inputting a shift control signal only one time. However, as the bit number of the barrel shifter increases the number of transfer gates as well as that of bit shift control lines increases, resulting in difficulty in miniaturization. Furthermore, the data input line, the data output line, the bit shift control line, and the transfer gate cross with each other, similarly resulting in difficulty in miniaturization. Furthermore, in order to conduct a shift as shown in FIG. 7(c) an increase in the number of transfer gates and an addition of bit line control lines are required resulting in a large sized device.
Another prior art barrel register is disclosed in an article "Introduction to VLSI Systems" by CARVER MEAD, LYNN CONWAY, ADDISON WESLEY PUBLISHING COMPANY, Second Printing, October, 1980. In this article FIG. 5, 14 shows an example of a 4-input, 4-output barrel shifter, wherein there is provided a cross-bar switch for connecting each of the inputs to each of the outputs.